1. Field of the Invention
The present invention relates to a semiconductor device including a MOS semiconductor element, and in particular, to a semiconductor device including a MOS semiconductor element having a high withstand voltage.
2. Description of the Related Art
In order to realize a high drain withstand voltage in a MOS semiconductor element having a MOS transistor structure of a semiconductor device, an electric field in the vicinity of the drain needs to be relaxed. One method of realizing electric field relaxation in the vicinity of a drain is to form a so-called LOCOS-drain type MOS transistor in which a thick oxide film (field oxide film) is formed by LOCOS in the vicinity of the drain.
FIG. 2 is a sectional view of a LOCOS-drain type MOS transistor. A heavily doped n-type diffusion layer 5 serving as a source region and a medium doped n-type diffusion layer 2 serving as a drain region are formed in a surface of a p-type silicon substrate 1 so as to be separated from each other. If a thick gate oxide film is formed in a channel region between the heavily doped n-type diffusion layer 5 and the medium doped n-type diffusion layer 2, current drivability is lowered, and thus, instead of the thick gate oxide film, a thin gate oxide film 6A is formed. A LOCOS oxide film 7, which is a thick oxide film, is formed on the medium doped n-type diffusion layer 2 serving as the drain region. A gate electrode 8 is formed so as to extend from the thin gate oxide film 6A on the channel region to the LOCOS oxide film 7. A heavily doped n-type diffusion layer 4 is formed adjacent to the medium doped n-type diffusion layer 2 for connection to a metal layer, and a thin oxide film on a drain (hereinafter referred to as drain oxide film) 6B is formed on a surface of the heavily doped n-type diffusion layer 4.
There are cases in which a lightly doped n-type diffusion layer 3 is further formed under the medium doped n-type diffusion layer 2 and the heavily doped n-type diffusion layer 4 serving as the drain region. The lightly doped n-type diffusion layer 3 may be formed as an n-type well region. The LOCOS oxide film 7 is formed primarily for the purpose of isolating elements, and is, in this case, applied to a drain of a high withstand voltage MOS transistor, which is a method of realizing a high withstand voltage MOS transistor without increasing the number of manufacturing steps. Note that, in FIG. 2, a region denoted as N+ means that the region has an impurity concentration higher than that of a region denoted as N±. A region denoted as N± means that the region has an impurity concentration higher than that of a region denoted as NWELL.
Various attempts have been made to a LOCOS-drain type MOS transistor, such as reduction of fluctuations in drain withstand voltage (see, for example, Japanese Patent Application Laid-open No. 2002-329728).
In designing an integrated circuit having a LOCOS-drain type MOS transistor mounted thereon, it is desired that the length of the LOCOS oxide film 7 in a channel direction in the vicinity of a drain be as short as possible. However, if the length is small, when a polysilicon film serving as a gate electrode is patterned in a process of manufacturing the integrated circuit, misalignment may be produced to form an undesirable pattern.
FIG. 3 is an illustration of such poor pattern formation. A gate electrode 8 formed of a polysilicon film should come up to a flat portion of an upper surface of the LOCOS oxide film 7. In the case of poor pattern formation, the gate electrode 8 is sometimes located beyond the LOCOS oxide film 7 to reach a thin drain oxide film 6B formed on the heavily doped region 4 on a drain side. A reference numeral 12 in FIG. 3 designates such a gate electrode that extends to the thin drain oxide film 6B. A large potential difference is applied between the drain region and the gate electrode. In such a structure, the drain oxide film 6B under the gate electrode that reaches the heavily doped region 4 on the drain side is thin and has only a low withstand voltage, and thus, the LOCOS-drain type MOS transistor cannot have a withstand voltage that is originally desired, resulting in a poor withstand voltage.